<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>LDR (immediate, SIMD&amp;FP) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">LDR (immediate, SIMD&amp;FP)</h2>
      <p class="aml">Load SIMD&amp;FP Register (immediate offset). This instruction loads an element from memory, and writes the result as a scalar to the SIMD&amp;FP register. The address that is used for the load is calculated from a base register value, a signed immediate offset, and an optional offset that is a multiple of the element size.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 3 classes:
      <a href="#iclass_post_indexed">Post-index</a>
      , 
      <a href="#iclass_pre_indexed">Pre-index</a>
       and 
      <a href="#iclass_unsigned_scaled_offset">Unsigned offset</a>
    </p>
    <h3 class="classheading"><a id="iclass_post_indexed"/>Post-index</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td colspan="2" class="lr">size</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td class="l">x</td><td class="r">1</td><td class="lr">0</td><td colspan="9" class="lr">imm9</td><td class="l">0</td><td class="r">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="3"/><td/><td colspan="2"/><td colspan="2" class="droppedname">opc</td><td/><td colspan="9"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">8-bit<span class="bitdiff"> (size == 00 &amp;&amp; opc == 01)</span></h4><a id="LDR_B_ldst_immpost"/><p class="asm-code">LDR  <a href="#sa_bt" title="8-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Bt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a></p></div><div class="encoding"><h4 class="encoding">16-bit<span class="bitdiff"> (size == 01 &amp;&amp; opc == 01)</span></h4><a id="LDR_H_ldst_immpost"/><p class="asm-code">LDR  <a href="#sa_ht" title="16-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Ht&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a></p></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (size == 10 &amp;&amp; opc == 01)</span></h4><a id="LDR_S_ldst_immpost"/><p class="asm-code">LDR  <a href="#sa_st" title="32-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;St&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a></p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (size == 11 &amp;&amp; opc == 01)</span></h4><a id="LDR_D_ldst_immpost"/><p class="asm-code">LDR  <a href="#sa_dt" title="64-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Dt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a></p></div><div class="encoding"><h4 class="encoding">128-bit<span class="bitdiff"> (size == 00 &amp;&amp; opc == 11)</span></h4><a id="LDR_Q_ldst_immpost"/><p class="asm-code">LDR  <a href="#sa_qt" title="128-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Qt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a></p></div><p class="pseudocode">boolean wback = TRUE;
boolean postindex = TRUE;
integer scale = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(opc&lt;1&gt;:size);
if scale &gt; 4 then UNDEFINED;
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64);</p>
    <h3 class="classheading"><a id="iclass_pre_indexed"/>Pre-index</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td colspan="2" class="lr">size</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td class="l">x</td><td class="r">1</td><td class="lr">0</td><td colspan="9" class="lr">imm9</td><td class="l">1</td><td class="r">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="3"/><td/><td colspan="2"/><td colspan="2" class="droppedname">opc</td><td/><td colspan="9"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">8-bit<span class="bitdiff"> (size == 00 &amp;&amp; opc == 01)</span></h4><a id="LDR_B_ldst_immpre"/><p class="asm-code">LDR  <a href="#sa_bt" title="8-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Bt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a>]!</p></div><div class="encoding"><h4 class="encoding">16-bit<span class="bitdiff"> (size == 01 &amp;&amp; opc == 01)</span></h4><a id="LDR_H_ldst_immpre"/><p class="asm-code">LDR  <a href="#sa_ht" title="16-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Ht&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a>]!</p></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (size == 10 &amp;&amp; opc == 01)</span></h4><a id="LDR_S_ldst_immpre"/><p class="asm-code">LDR  <a href="#sa_st" title="32-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;St&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a>]!</p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (size == 11 &amp;&amp; opc == 01)</span></h4><a id="LDR_D_ldst_immpre"/><p class="asm-code">LDR  <a href="#sa_dt" title="64-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Dt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a>]!</p></div><div class="encoding"><h4 class="encoding">128-bit<span class="bitdiff"> (size == 00 &amp;&amp; opc == 11)</span></h4><a id="LDR_Q_ldst_immpre"/><p class="asm-code">LDR  <a href="#sa_qt" title="128-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Qt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, #<a href="#sa_simm" title="Signed immediate byte offset [-256-255] (field &quot;imm9&quot;)">&lt;simm&gt;</a>]!</p></div><p class="pseudocode">boolean wback = TRUE;
boolean postindex = FALSE;
integer scale = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(opc&lt;1&gt;:size);
if scale &gt; 4 then UNDEFINED;
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64);</p>
    <h3 class="classheading"><a id="iclass_unsigned_scaled_offset"/>Unsigned offset</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td colspan="2" class="lr">size</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td class="r">1</td><td class="l">x</td><td class="r">1</td><td colspan="12" class="lr">imm12</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="3"/><td/><td colspan="2"/><td colspan="2" class="droppedname">opc</td><td colspan="12"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">8-bit<span class="bitdiff"> (size == 00 &amp;&amp; opc == 01)</span></h4><a id="LDR_B_ldst_pos"/><p class="asm-code">LDR  <a href="#sa_bt" title="8-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Bt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_pimm" title="Optional positive immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;pimm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">16-bit<span class="bitdiff"> (size == 01 &amp;&amp; opc == 01)</span></h4><a id="LDR_H_ldst_pos"/><p class="asm-code">LDR  <a href="#sa_ht" title="16-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Ht&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_pimm_2" title="Optional positive immediate byte offset, multiple of 2 [0-8190], default 0 (field &quot;imm12&quot;)">&lt;pimm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (size == 10 &amp;&amp; opc == 01)</span></h4><a id="LDR_S_ldst_pos"/><p class="asm-code">LDR  <a href="#sa_st" title="32-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;St&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_pimm_4" title="Optional positive immediate byte offset, multiple of 4 [0-16380], default 0 (field &quot;imm12&quot;)">&lt;pimm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (size == 11 &amp;&amp; opc == 01)</span></h4><a id="LDR_D_ldst_pos"/><p class="asm-code">LDR  <a href="#sa_dt" title="64-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Dt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_pimm_1" title="Optional positive immediate byte offset, multiple of 8 [0-32760], default 0 (field &quot;imm12&quot;)">&lt;pimm&gt;</a>}]</p></div><div class="encoding"><h4 class="encoding">128-bit<span class="bitdiff"> (size == 00 &amp;&amp; opc == 11)</span></h4><a id="LDR_Q_ldst_pos"/><p class="asm-code">LDR  <a href="#sa_qt" title="128-bit SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Qt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{, #<a href="#sa_pimm_3" title="Optional positive immediate byte offset, multiple of 16 [0-65520], default 0 (field &quot;imm12&quot;)">&lt;pimm&gt;</a>}]</p></div><p class="pseudocode">boolean wback = FALSE;
boolean postindex = FALSE;
integer scale = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(opc&lt;1&gt;:size);
if scale &gt; 4 then UNDEFINED;
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 64), scale);</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Bt&gt;</td><td><a id="sa_bt"/>
        
          <p class="aml">Is the 8-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Dt&gt;</td><td><a id="sa_dt"/>
        
          <p class="aml">Is the 64-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ht&gt;</td><td><a id="sa_ht"/>
        
          <p class="aml">Is the 16-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Qt&gt;</td><td><a id="sa_qt"/>
        
          <p class="aml">Is the 128-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;St&gt;</td><td><a id="sa_st"/>
        
          <p class="aml">Is the 32-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;simm&gt;</td><td><a id="sa_simm"/>
        
          <p class="aml">Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;pimm&gt;</td><td><a id="sa_pimm"/>
        
          
          
          
        
        
          <p class="aml">For the 8-bit variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_pimm_2"/>
        
          
          
          
        
        
          <p class="aml">For the 16-bit variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as &lt;pimm&gt;/2.</p>
        
      </td></tr><tr><td/><td><a id="sa_pimm_4"/>
        
          
          
          
        
        
          <p class="aml">For the 32-bit variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as &lt;pimm&gt;/4.</p>
        
      </td></tr><tr><td/><td><a id="sa_pimm_1"/>
        
          
          
          
        
        
          <p class="aml">For the 64-bit variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as &lt;pimm&gt;/8.</p>
        
      </td></tr><tr><td/><td><a id="sa_pimm_3"/>
        
          
          
          
        
        
          <p class="aml">For the 128-bit variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as &lt;pimm&gt;/16.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="postdecode"/><h3 class="pseudocode">Shared Decode</h3>
      <p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
<a href="shared_pseudocode.html#MemOp" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if opc&lt;0&gt; == '1' then <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a href="shared_pseudocode.html#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
integer datasize = 8 &lt;&lt; scale;
boolean tagchecked = memop != <a href="shared_pseudocode.html#MemOp_PREFETCH" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a> &amp;&amp; (wback || n != 31);</p>
    </div>
  
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPEnabled64.0" title="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
bits(64) address;
bits(datasize) data;

<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescASIMD.3" title="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, FALSE, tagchecked);

if n == 31 then
    <a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

if !postindex then
    address = address + offset;

case memop of
    when <a href="shared_pseudocode.html#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
        data = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[t, datasize];
        <a href="shared_pseudocode.html#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccessDescriptor accdesc] = bits(size*8) value_in">Mem</a>[address, datasize DIV 8, accdesc] = data;

    when <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
        data = <a href="shared_pseudocode.html#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, datasize DIV 8, accdesc];
        <a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = data;

if wback then
    if postindex then
        address = address + offset;
    if n == 31 then
        <a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = address;
    else
        <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</p>
    </div>
  <h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</p>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
